The present invention relates to a method for etching contacts through layers of an integrated circuit and, in particular, to a self aligned contact (SAC) etch using a dual-chemistry process.
The current semiconductor industry poses an ever-increasing pressure for achieving higher device density within a given die area. This is particularly true in memory circuit fabrication, for example DRAM (Dynamic Random Access Memory) manufacture. Each memory cell of a DRAM consists of a single capacitor and a field effect transistor as a charge transfer transistor. The binary data is stored as electrical charge on the capacitor in the individual memory cells. In recent years, the number and density of these memory cells on the DRAM chip has dramatically increased so that the number of memory cells on a single chip is expected to soon reach 1 Gigabit.
The increase in circuit density is the result of the downsizing of the individual semiconductor devices (MOSFETs) and increasing in device packing density. The reduction in device size is due partly to the advances in photolithography and directional (anisotropic) plasma etching. As the horizontal device feature sizes continue to go down to submicrometer dimensions, it is necessary to use self-alignment techniques to relax the alignment requirements and improve critical dimension (CD) control. One such technique is called a self-aligned contact (SAC) etch, in which a pair of adjacent gate s are utilized to align an etched opening in an insulating layer.
The increase in device packing density also places increasing demands on many aspects of the fabrication process. Alignment of features from one level to the next is of critical importance, particularly the alignment of contact holes with underlying structures, for example an active area, with which they are to connect. The miniaturization of the devices makes difficult the formation of interconnect structures in that, in order to maintain sufficient electrical communication, the interconnect structure must be formed in exact alignment with an underlying active region. At the same time, the area of the interconnect structure interfacing with the active area must be maximized. Thus, as device sizes shrink there is less room for misalignment errors of the interconnect structure.
The miniaturization of DRAM devices often requires SAC etch processes, which primarily involve dry etches or plasma etches. Almost all of the current dry etch technology for SAC etch processes uses a CxFy (x greater than 1)-type plasma chemistry, such as, for example, C4F8, C5F8, or C4F6 in combination with other diluent gases.
Although the CxFy type chemistry offers very high selectivity to the silicon nitride cap and silicon nitride spacers, which are the most typical etch stop material for gate stack protection in a SAC etch, it has the disadvantage that it has a very small process window. This is primarily due to the fact that the CxFy-type chemistry generates a fluorocarbon polymer which is more carbon rich than the polymers generated with other types of chemistry. With this very carbon-rich fluorocarbon polymer, the etch often results in etch stop condition, a situation when etching stops before reaching the substrate, when the gas flow is off even by a small amount from the optimal setting.
The use of conventional CxFy-type chemistry has an additional drawback, in that it does not offer any significant selectivity to the field oxide barriers formed by isolation techniques such as STI or LOCOS processes. As an example, the need to not etch the silicon nitride cap during the SAC process demands selective oxide-to-nitride etch conditions, while the need to not etch into the undoped silicon oxide of field oxide regions requires etch selectivity between doped and undoped oxide. These are typically mutually exclusive.
These simultaneous process requirements, which trend in opposing directions, may result in the penetration and damage of the field oxide regions adjacent to the active regions during the etching of the contact holes when oxide-to-nitride selective etch conditions are present and where there is slight misalignment of the location of the holes during the SAC etch process. As a result, the geometry of the STI or LOCOS regions is altered and the overall performance of the semiconductor device being fabricated degraded.
To illustrate this point, FIG. 1 depicts a conventional memory cell construction for a DRAM at an intermediate stage of the fabrication. A pair of memory cells having respective access transistors are formed within a substrate. The wells and transistors are surrounded by a field oxide region 14 that provides isolation. N-type active regions 16 are provided in a doped p-type well 12 of substrate 10 (for NMOS transistors) and the pair of access transistors have respective gate stacks 30.
An insulating layer 24 of, for example, BPSG has been applied over the substrate and transistor structures and a mask layer 26 having openings for etching the insulating layer to form contact openings to active regions 16 are also shown. Theoretically, the mask 26 is properly aligned to enable a SAC etch of the insulating layer 24 to provide contact openings down to the active regions 16.
Because of the nature of a SAC etch, slight misalignment of mask 26 in the left or right directions, as shown by the arrows A in FIG. 1, can be tolerated and allow production of a contact hole which exposes the active areas 16. However, mask 26 misalignment errors in a direction into and out of the FIG. 1 depiction, that is, in the directions B of FIG. 2, can cause a subsequent etch of the insulating layer 24 to produce a contact hole 40 (FIG. 2) which partially overlies the field oxide layer 14. Since the CxFy chemistry that etches the insulating layer 24 is not selective to the undoped silicon dioxide forming the field oxide layer 14, etching the contact hole 40 will also result in an undesirable etching of the field oxide layer 14 in the damage region 15.
Ideally, when the contact opening 40 is well aligned with respect to the active area 16 of the substrate 12, field oxide regions 14 are not exposed to the etch chemistry used during the SAC process necessary for the formation of contact opening 40. In practice, however, normal alignment tolerances occur often and thus the field oxide regions are often unavoidably exposed to the etch. Thus, etching through a doped oxide layer with a CxFy-type chemistry to create a self-aligned contact would inevitably etch into and damage the field oxide regions.
Under the prior art, attempts to minimize damage areas caused by the illustrated misalignment, such as damage region 15, have been mainly directed towards controlling the etch selectivity, that is trying to achieve etch chemistry that etches the BPSG, does not etch the silicon nitride caps and spacers 32 of the gate stacks, and does not etch the field oxide regions 14. This has been accomplished by varying the gas phase chemistry through adjustments in the plasma reactor gases or the operating pressure. For example, U.S. patent application Ser. No. 08/846,671, entitled xe2x80x9cUndoped Silicon Dioxide as an Etch Stop for Selective Etch of Doped Silicon Dioxide,xe2x80x9d the disclosure of which is incorporated herein by reference, discloses the use of hydrogen-containing fluorocarbon gas chemistry to achieve selectivity between doped silicon oxide and undoped silicon oxide.
Although the above referenced patent application discloses an improved method for achieving selectivity between doped and undoped silicon oxide, there is still room for an improved etching regime, which has the ability to operate under a wide range of aspect ratios and which can properly etch through the dielectric layer covering the gate stacks without damaging the underlying field oxide regions.
The present invention provides a plasma etching process for etching through a selected portion of a doped oxide layer, for example BPSG, on a substrate to create a self-aligned contact without damaging underlying field oxide regions.
The present method includes a first etching step for etching only partially through the doped oxide by employing a first chemistry and a first set of process parameters. The first chemistry uses essentially a CxFy (x greater than 1) chemistry, which has a very good selectivity to the silicon nitride cap and silicon nitride spacers provided on the gate stack structures, but which unfortunately has a poor selectivity to field oxide isolation regions. The first step etch is terminated before the doped oxide is etched all the way.
The present invention further includes a second etching step for etching the doped oxide layer through to the underlying silicon layer, with a second chemistry comprising an hydrogen-containing fluorocarbon chemistry and a second set of process parameters. Unlike the first chemistry, however, the hydrogen-containing fluorocarbon chemistry provides a very good selectivity to field oxide isolation regions, while it retains enough nitride selectivity to the gate stack to be capable of etch completion down to the silicon substrate. Thus, the method of the present invention allows the etching of the doped oxide dielectric layer, self-aligned to the gate stacks, without substantially damaging the nitride layer of the gate stack or any misaligned underlying field oxide isolation regions.
The second etch step is performed immediately following the end of the first step. The second etch step could be done by removing the wafer from the etch chamber where the first step is performed, and then transferring the wafer to a different chamber for the second step. Alternatively, the first and second steps could be done xe2x80x9cinsituxe2x80x9d without breaking the vacuum of the etch chamber or removing the wafer from the etch chamber.
It should be noted that although the invention is described below as employing a two-step etching process, it is also possible to use additional etching steps prior and subsequent to the described two-step process.
Additional advantages and features of the present invention will be more apparent from the detailed description and accompanying drawings, which illustrate preferred embodiments of the invention.